fpga-sigma-delta-dac
yunochi
FPGA로 만드는 자작 오디오 DAC 프로젝트
Components (22)
| Reference | Value | Description |
|---|---|---|
| U1 | LM27762 | Low-noise inverting charge pump with both positive and negative LDO's, with 2.7V-5.5V input to +1.5 to +5V and -1.5 to -5V Output Voltage, WSON-12 |
| U2,U3 | SN74LVC1G125DBV | Single Buffer Gate Tri-State, Low-Voltage CMOS, SOT-23-5 |
| U4 | OPA1688IDR | Dual Operational Amplifiers, SOIC-8/TSSOP-8/VSSOP-8 |
| C1,C3 | 4.7 uF | 1608 10V X7R |
| C2 | 1uF | 16V 1005 X5R |
| C4,C5 | 2.2uF | 16V X5R 1005 |
| C6,C9,C16-C19 | 100nF | 50V 1005 X7R |
| C7,C10 | 470nF | 25V C0G 5% 3216 |
| C8,C11,C12,C14 | 2.2nF | 1608 C0G 1% |
| C13,C15 | 1 nF | 1608 1% C0G |
| D1 | ESD9B5.0ST5G | ESD protection diode, 5.0Vrwm, SOD-923 |
| FB1,FB2 | FerriteBead | 2012 600Ohm@100MHz BLM21PG601SN1D |
| J1 | AudioJack3_SwitchTR | Audio Jack, 3 Poles (Stereo / TRS), Switched TR Poles (Normalling) |
| J2 | Conn_02x03_Top_Bottom | Generic connector, double row, 02x03, top/bottom pin numbering scheme (row 1: 1...pins_per_row, row2: pins_per_row+1 ... num_pins), script generated (kicad-library-utils/schlib/autogen/connector/) |
| R1,R2,R7,R9 | 330 | 1608 1% |
| R3 | 187 k | 1608 1% |
| R4,R5 | 107 k | 1608 1% |
| R6 | 182 k | 1608 1% |
| R8,R10 | 100k | 1608 1% |
| R11,R14 | 2.61k | 1608 1% |
| R12,R15 | 4.87k | 1608 1% |
| R13,R16 | 0 | 2012 5% |