dmg-schematics
msinger
Reverse engineered schematics of the Game Boy's DMG-CPU B chip
Components (87)
| Reference | Value | Description |
|---|---|---|
| U1,U2,U7,U?,U?,U?,U?,U?,U?,U?,U?,U?,U?,U?,U?,U?,U?,U?,U?,U?,U?,U?,U?,U?,U?,U?,U?,U?,U?,U?,U?,U?,U?,U?,U?,U?,U?,U?,U?,U?,U?,U?,U?,U?,U?,U?,U?,U?,U?,U?,U?,U?,U?,U?,U?,U?,U?,U?,U?,U?,U?,U?,U?,U?,U?,U?,U?,U?,U?,U?,U?,U?,U?,U?,U?,U?,U?,U?,U?,U?,U?,U? | NOT_X1 | Simple inverter. |
| U4,U6,U?,U?,U?,U?,U?,U?,U?,U?,U?,U?,U?,U?,U?,U?,U? | NOT_IF1 | Tri-state inverter with active-high enable input. |
| U5,U8,U?,U?,U?,U?,U?,U?,U? | NOT_IF0 | Tri-state inverter with active-low enable input. |
| U9,U?,U?,U?,U? | AND3 | AND gate with three inputs. |
| U? | NAND8_OD | Open-drain NAND gate with eight inputs. |
| U?,U?,U?,U?,U?,U?,U?,U?,U?,U?,U?,U?,U?,U?,U?,U?,U? | BUF_IF1_OD | Open-drain buffer with active-high enable input. |
| U? | MUX_IDU_H | Multiplexer with two inputs. |
| U? | PCH_DEC2_A | Simple PMOS transistor for precharging. |
| U? | NOR2_IN2_N | NOR gate with two inputs, one of them inverted. |
| U? | OA211_IN1_N_IN3_N | 2-1-1 OR-AND two-level compound gate with inverted IN1 and IN3. |
| U? | NOR2_OS | Open-source NOR gate with two inputs. |
| U? | B2B_WAND_INJ_A | Bidirectional bus bridge with wired-AND behavior (open-drain), active-low output enable, active-low precharge, and open-drain injector on side A. |
| U? | NAND6_OD | Open-drain NAND gate with six inputs. |
| U? | OR2_OD | Open-drain OR gate with two inputs. |
| U? | AO31_IN3_N | 3-1 AND-OR two-level compound gate with inverted IN3. |
| U? | SRLATCH_R_N_ALT | SR-latch with active-high set input and active-low reset input. Reset takes precedence when both inputs are asserted. |
| U? | NAND2_IN1_N_A | NAND gate with two inputs, one of them inverted. |
| U? | DFFN_EE_Q_ALU_SIGN | Semi-dynamic data flip-flop with externally inverted enable inputs, level-sensitive D-gating, and no inverted output. |
| U?,U? | NOT_IF11 | Tri-state inverter with two active-high enable inputs. |
| U? | DFF_CC_EE_Q_N_REG_WZ_BIT | Semi-dynamic data flip-flop with complementary clock inputs, externally inverted enable inputs, level-sensitive D-gating, and no non-inverted output. |
| U? | DFFR_CC_EE_REG_IE_BIT | Semi-dynamic data flip-flop with complementary clock inputs, externally inverted enable inputs, level-sensitive D-gating, and active-high reset gated by the clock level. |
| U? | MUX_IDU_L | Multiplexer with two inputs. |
| U? | DLATCH_EE_IRQ | Gated data latch with externally inverted enable inputs and additional dynamically controlled inverted output. |
| U? | AO22222 | 2-2-2-2-2 AND-OR two-level compound gate. |
| U? | BUF_IF11_OD | Open-drain buffer with two active-high enable inputs. |
| U? | NAND_2_OS | |
| U? | NAND4_OD | Open-drain NAND gate with four inputs. |
| U? | BUF_IF00 | Tri-state buffer with two active-low enable inputs. |
| U? | NAND9_OD | Open-drain NAND gate with nine inputs. |
| U? | DFF_CC_EE_Q_X1_REG_BIT | Semi-dynamic data flip-flop with complementary clock inputs, externally inverted enable inputs, level-sensitive D-gating, and no inverted output. |
| U? | DFF_CC_EE_Q_X2_REG_BIT | Semi-dynamic data flip-flop with complementary clock inputs, externally inverted enable inputs, level-sensitive D-gating, 2× drive strength, and no inverted output. |
| U? | BUF_IF11 | Tri-state buffer with two active-high enable inputs. |
| U? | AOI21_IF1_OD | Open-drain 2-1 AND-OR-INVERT two-level compound gate with active-high enable input. |
| U? | NAND5_OD | Open-drain NAND gate with five inputs. |
| U? | NAND7_OD | Open-drain NAND gate with seven inputs. |
| U? | ALU_CGEN | Logic for generating carry signals for the CLA (carry lookahead adder). |
| U?,U?,U?,U? | OAI21_OS | Open-source 2-1 OR-AND-INVERT two-level compound gate. |
| U? | AO2222 | 2-2-2-2 AND-OR two-level compound gate. |
| U?,U?,U?,U?,U?,U? | AO222 | 2-2-2 AND-OR two-level compound gate. |
| U? | DFFN_EE_PCH_D_ALU_FLAG | Semi-dynamic data flip-flop with externally inverted enable inputs, level-sensitive D-gating, and prechargable D input. |
| U? | DFF_CC_EE_PCH_D_REG_SP_BIT | Semi-dynamic data flip-flop with complementary clock inputs, externally inverted enable inputs, level-sensitive D-gating, and prechargable D input. |
| U? | DFFS_CC_EE_PCH_D_REG_PC_BIT | Semi-dynamic data flip-flop with complementary clock inputs, externally inverted enable inputs, level-sensitive D-gating, prechargable D input, and active-low set gated by the clock level. |
| U?,U? | NOR2_OD | Open-drain NOR gate with two inputs. |
| U? | OAI21 | 2-1 OR-AND-INVERT two-level compound gate. |
| U?,U? | AO221 | 2-2-1 AND-OR two-level compound gate. |
| U?,U?,U? | XOR_IDU_L | XOR gate with two inputs. |
| U?,U?,U?,U?,U?,U?,U?,U?,U?,U?,U?,U?,U?,U? | NAND2 | NAND gate with two inputs. |
| U?,U?,U?,U?,U?,U?,U?,U?,U?,U?,U?,U?,U?,U?,U?,U?,U?,U?,U?,U?,U?,U?,U?,U?,U?,U?,U?,U?,U?,U?,U?,U?,U?,U?,U?,U?,U?,U?,U?,U?,U?,U?,U?,U?,U?,U?,U?,U?,U?,U?,U?,U?,U? | BUF_IF0 | Tri-state buffer with active-low enable input. |
| U? | AOI44_OD | Open-drain 4-4 AND-OR-INVERT two-level compound gate. |
| U?,U?,U?,U?,U?,U?,U? | AO21 | 2-1 AND-OR two-level compound gate. |
| U?,U?,U?,U?,U?,U?,U?,U?,U?,U? | OA21 | 2-1 OR-AND two-level compound gate. |
| U? | AO33 | 3-3 AND-OR two-level compound gate. |
| U? | NOR4_IN2_N_IN4_N | NOR gate with four inputs, two of them inverted. |
| U? | DLATCH_EE_Q_N | Gated data latch with externally inverted enable inputs and no non-inverted output. |
| U?,U?,U?,U?,U? | AOI33_OD | Open-drain 3-3 AND-OR-INVERT two-level compound gate. |
| U?,U?,U? | AO22 | 2-2 AND-OR two-level compound gate. |
| U? | AOI331_S3 | 3-3-1 AND-OR-INVERT two-level compound gate with shared IN3. |
| U? | SRLATCH_R_N | SR-latch with active-high set input and active-low reset input. Reset takes precedence when both inputs are asserted. |
| U?,U?,U?,U?,U?,U?,U?,U?,U?,U?,U?,U?,U?,U?,U?,U?,U?,U?,U?,U?,U?,U?,U?,U?,U?,U?,U?,U?,U?,U?,U?,U?,U?,U?,U?,U?,U?,U?,U?,U?,U?,U?,U?,U?,U?,U?,U?,U?,U?,U?,U?,U?,U?,U? | NAND2_OD | Open-drain NAND gate with two inputs. |
| U?,U?,U?,U?,U?,U?,U?,U?,U?,U?,U?,U? | AOI22_OD | Open-drain 2-2 AND-OR-INVERT two-level compound gate. |
| U?,U?,U?,U?,U?,U?,U? | AOI21_OD | Open-drain 2-1 AND-OR-INVERT two-level compound gate. |
| U? | DFF_CC_Q_ALT | Single-edge-triggered data flip-flop with complementary clock inputs and no inverted output. |
| U? | DFF_CC_Q | Single-edge-triggered data flip-flop with complementary clock inputs and no inverted output. |
| U?,U?,U? | NAND3_OD | Open-drain NAND gate with three inputs. |
| U?,U? | AOI222_OD | Open-drain 2-2-2 AND-OR-INVERT two-level compound gate. |
| U? | OAI31_OD | Open-drain 3-1 OR-AND-INVERT two-level compound gate. |
| U? | OAI21_OD | Open-drain 2-1 OR-AND-INVERT two-level compound gate. |
| U?,U? | MUXI | |
| U? | AO221_IN5_N | 2-2-1 AND-OR two-level compound gate with inverted IN5. |
| U?,U?,U? | NAND3 | NAND gate with three inputs. |
| U? | NOR8_ALU | NOR gate with eight inputs. |
| U?,U?,U?,U?,U?,U?,U?,U?,U? | BUF_IF1 | Tri-state buffer with active-high enable input. |
| U?,U?,U?,U?,U?,U?,U? | BUF_IF0_OS | Open-source buffer with active-low enable input. |
| U? | XOR_IDU_H | XOR gate with two inputs. |
| U? | NAND2_OD_A_DBUS | Open-drain NAND gate with two inputs. |
| U?,U?,U?,U?,U?,U?,U?,U?,U? | OR2 | OR gate with two inputs. |
| U? | AOI21_A | 2-1 AND-OR-INVERT two-level compound gate. |
| U? | OR3_A | OR gate with three inputs. |
| U?,U?,U?,U?,U?,U?,U?,U?,U?,U?,U?,U?,U?,U? | AND2 | AND gate with two inputs. |
| U? | NOR3 | NOR gate with three inputs. |
| U?,U?,U?,U?,U?,U? | NOT_IF01 | Tri-state inverter with one active-low and one active-high enable input. |
| U?,U?,U?,U?,U?,U?,U? | NOR2 | NOR gate with two inputs. |
| U? | DFFRE_CC_Q | Semi-dynamic data flip-flop with complementary clock inputs, level-sensitive D-gating, active-high reset gated by the clock level, and no inverted output. |
| C?,C?,C?,C?,C?,C?,C?,C?,C?,C?,C?,C?,C?,C?,C?,C? | C | |
| N1-N62 | NMOS | |
| P1-P28 | PMOS | |
| R1,R2,R?,R? | R | Resistor |