dmg-schematics
msinger
Reverse engineered schematics of the Game Boy's DMG-CPU B chip
Components (72)
| Reference | Value | Description |
|---|---|---|
| U? | DLATCH_EE | Gated data latch with externally inverted enable inputs. |
| U? | DLATCH | Gated data latch with active-high enable. |
| U? | MUXI | Inverting multiplexer with two inputs. |
| U? | NOT_X6 | Inverter with 6× drive strength. |
| U? | NAND5 | NAND gate with five inputs. |
| U? | NAND4 | NAND gate with four inputs. |
| U? | NOR4 | NOR gate with four inputs. |
| U? | NOR3 | NOR gate with three inputs. |
| U? | NOT_X2 | Inverter with 2× drive strength. |
| U? | NOR8 | NOR gate with eight inputs. |
| U? | NOT_IF1 | Tri-state inverter with active-high enable input. |
| U? | NAND3 | NAND gate with three inputs. |
| U? | MIXER | 5-channel analog mixer. |
| U? | NOR5 | NOR gate with five inputs. |
| U?,U? | DAC | 4-bit digital to analog converter. |
| U? | DFFR | Positive-edge-triggered data flip-flop with active-low asynchronous reset. |
| U? | PAD_PASS_TG | Simple pass pad with transmission gate. Used as analog input. |
| U? | PAD_PASS | Simple pass pad with direct metal connection. Used as analog output. |
| U? | RV | 3-bit digital rheostat. |
| U? | PAD_BIDIR_PU | Bidirectional pad with open-drain/-source capability and optional pull-up resistor. |
| U? | AO222222 | 2-2-2-2-2-2 AND-OR two-level compound gate. |
| U? | FULL_ADD | Full adder. |
| U? | PAD_BIDIR_PU_LATCH | Bidirectional pad with open-drain/-source capability, optional pull-up resistor, and input NAND latch. |
| U? | AO2222 | 2-2-2-2 AND-OR two-level compound gate. |
| U? | OA21 | 2-1 OR-AND two-level compound gate. |
| U? | AO222 | 2-2-2 AND-OR two-level compound gate. |
| U? | AO22 | 2-2 AND-OR two-level compound gate. |
| U? | DFFR_CC | Single-edge-triggered data flip-flop with complementary clock inputs and active-low asynchronous reset. |
| U? | VDIV | Voltage divider. |
| U? | AMP | CMOS differential amplifier with push-pull output. |
| U? | OR4 | OR gate with four inputs. |
| U? | NAND7 | NAND gate with seven inputs. |
| U? | NAND6 | NAND gate with six inputs. |
| U? | NOR6 | NOR gate with six inputs. |
| U? | BUF_IF0 | Tri-state buffer with active-low enable input. |
| U? | PAD_IN | Simple inverting input pad. |
| U? | PAD_IN_PU | Simple inverting input pad with pull-up resistor. |
| U?,U? | OR2 | OR gate with two inputs. |
| U? | AND3 | AND gate with three inputs. |
| U? | PAD_BIDIR | Bidirectional pad with open-drain/-source capability. |
| U? | AND4 | AND gate with four inputs. |
| U? | DFFSR | Positive-edge-triggered data flip-flop with active-low asynchronous set and reset. |
| U?,U?,U?,U?,U?,U?,U?,U?,U?,U?,U?,U?,U?,U? | AND2 | AND gate with two inputs. |
| U?,U?,U?,U?,U?,U?,U?,U?,U?,U?,U? | NOR2 | NOR gate with two inputs. |
| U?,U?,U?,U?,U?,U?,U?,U?,U?,U?,U?,U?,U?,U?,U?,U? | MUX | Multiplexer with two inputs. |
| U?,U?,U?,U?,U?,U?,U?,U?,U?,U?,U?,U?,U?,U?,U?,U?,U?,U?,U?,U?,U?,U?,U?,U?,U?,U?,U?,U?,U?,U?,U?,U? | NOT_X1 | Simple inverter. |
| U? | DLATCH_EE_Q | Gated data latch with externally inverted enable inputs and no inverted output. |
| U? | NOT_X4 | Inverter with 4× drive strength. |
| U?,U?,U?,U? | XOR | XOR gate with two inputs. |
| U? | PAD_OUT_DIFF | Output pad with open-drain/-source capability. |
| U? | OR3 | OR gate with three inputs. |
| U? | HALF_ADD | Half adder. |
| U? | PAD_OUT | Simple inverting output pad. |
| U? | DFFR_CC_Q | Single-edge-triggered data flip-flop with complementary clock inputs, active-low asynchronous reset, and no inverted output. |
| U? | PAD_XTAL | Oscillator input and output pads for connecting external crystal. |
| U? | TFFNL | Negative-edge-triggered toggle flip-flop with active-high asynchronous data load. |
| U?,U? | OAI21 | 2-1 OR-AND-INVERT two-level compound gate. |
| U?,U?,U?,U?,U?,U?,U?,U?,U? | NAND2 | NAND gate with two inputs. |
| U? | XNOR | XNOR gate with two inputs. |
| U?,U?,U?,U? | AO21 | 2-1 AND-OR two-level compound gate. |
| U? | NOT_IF0 | Tri-state inverter with active-low enable input. |
| U? | DRLATCH_EE | Gated data latch with externally inverted enable inputs and active-low reset. |
| U? | NOT_X3 | Inverter with 3× drive strength. |
| C1 | C | Unpolarized capacitor |
| D1-D7 | D | |
| N1-N70,N?,N?,N?,N?,N?,N?,N?,N?,N?,N?,N?,N?,N?,N?,N?,N?,N?,N?,N?,N? | NMOS | |
| P1-P69,P?,P? | PMOS | |
| R1-R33 | R | |
| R2 | 20k,R | |
| TP?,TP? | XO | |
| TP?,TP? | XI | |
| TP?,TP?,TP?,TP?,TP?,TP?,TP?,TP?,TP?,TP? | Bonding Pad |