Code-SDR
iamdarshg
hardware and software implementations for a FPGA based ultra-wideband software deifned radio
Components (107)
| Reference | Value | Description |
|---|---|---|
| U1,U2 | TLV62569DBVR | 2 A synchronous 1.2 V core buck,2 A synchronous 3.3 V digital buck |
| U3 | TLV75525PDBVR | 500 mA high-PSRR 2.5 V auxiliary LDO |
| U4 | TLV76733DRVR | 1 A low-noise/high-PSRR 3.3 V analog LDO |
| U10 | RP2040 | Control processor only; no ESC or motor-power functions |
| U11 | W25Q16JVSSIQ | 16 Mbit QSPI boot flash |
| U12 | USBLC6-2SC6 | Low-capacitance USB ESD protection; paired flow-through pins stay on the connector side of the 27 ohm series resistors |
| U20 | LIF-MD6000-6JMG80I | 0.65 mm pitch CrossLink package; enough I/O for ADC plus RGMII without HDI-only 0.4 mm UMG64 |
| U21 | AD9215BCPZ-105 | 10-bit ADC operated at 100 MSPS (105 MSPS maximum); DNC pins intentionally floating |
| U30 | KSZ9031RNXCA | Gigabit RGMII PHY using external 1.2 V rail; LDO_O left floating |
| U40 | LMX2592RHAT | 20 MHz to 9.8 GHz first LO; both outputs biased per data sheet |
| U41 | ADF4360-1BCPZ | Fixed 2.410 GHz integer-N second LO: 100 MHz/R20, P16, B30, A2 |
| U42 | CDCLVC1104PWR | Low-additive-jitter 1:4 LVCMOS fanout; one output intentionally unused |
| U50,U60 | GRF4001 | 2.3_4.2GHz internally matched broadband low-noise branch, 3.3 V/45 mA,Internally matched 0.1-6 GHz LNA; 3.3 V/45 mA cost-first low-noise stage |
| U51 | ADL5801ACPZ-R7 | Low-band first mixer; differential 2.43625 GHz IF |
| U61,U62,U66,U67 | GRF2101 | 4.2_6.8GHz manufacturer-characterized GRF2101 match; inactive branch is disabled,6.8_9.2GHz manufacturer-characterized GRF2101 match; inactive branch is disabled,8.0_10GHz manufacturer-characterized GRF2101 match; inactive branch is disabled,Second 8-10 GHz D-port LNA; improves top-band NF at minimal BOM cost |
| U63 | LTC5548IUDB | 2-14 GHz high-linearity first mixer, X2 disabled |
| U64 | QPC6144TR13 | 50 MHz to 12 GHz high-isolation SP4T after the branch LNAs; LC0/LC1 low select 1.8 V logic and V3/VSS are grounded |
| U70 | BGS12WN6E6327 | First-IF low/high path selector at 2.43625 GHz |
| U71,U75 | GRF2013 | 2.4 GHz IF gain block using the released data-sheet 5 V/90 mA 0.7-3.8 GHz tune,Second 2.4 GHz IF gain block after the fail-safe DSA; restores 10-bit ADC quantization margin on the 8-10 GHz worst-case path |
| U72 | PE4312C-Z | Active 1 MHz-4 GHz, 0.5 dB-step, 31.5 dB serial DSA; powers up at maximum attenuation |
| U73 | LT5560EDD | 2.410 GHz second mixer producing 26.25 MHz center IF |
| U74 | AD8351ARMZ | Low-distortion differential ADC driver; gain set for AD9215 full scale |
| C1,C2,C4,C7 | 22uF | +1V2_CORE local bypass,+3V3_DIG local bypass,+5V_RF local bypass,VIN_FUSED local bypass |
| C3,C6,C41,C43,C45,C56-C58,C61,C62,C65-C67,C73,C83,C94,C106,C154,C155,C159,C261,C279-C281,C297,C300,C310 | 10uF | +1V2_CORE local bypass,+3V3_ANA local bypass,+3V3_DIG local bypass,+5V_RF local bypass,ADC_REFB local bypass,ADC_REFT local bypass,ADC_VREF local bypass,ADF4360-1 CN compensation capacitor to VVCO,FPGA_VCC_1V2 local bypass,LMX_VARAC local bypass,LMX_VBIAS1 local bypass,LMX_VREF local bypass,LMX_VREF2 local bypass,PHY_AVDDH_3V3 local bypass,PHY_AVDDL_1V2 local bypass,PHY_PLL_1V2 local bypass,VIN_FUSED local bypass |
| C5,C8,C23-C28,C40,C42,C44,C46-C48,C50-C55,C60,C69,C71,C76-C78,C81,C82,C93,C100,C101,C105,C150-C153,C174,C200,C214,C224-C227,C254-C256,C260,C270,C272-C278,C283,C284,C293,C295,C296,C298,C299,C302-C309,C311,C312,C314,C316,C318,C319,C321,C322 | 100nF | +1V2_CORE local bypass,+3V3_ANA local bypass,+3V3_DIG local bypass,+5V_RF local bypass,AD8351 INHI AC coupling,AD8351 INLO AC coupling,ADC_REFB local bypass,ADC_REFT local bypass,ADC_VCM local bypass,ADC_VREF local bypass,ADL_DETO local bypass,FPGA_PLL_1V2 local bypass,FPGA_VCCIO0_3V3 local bypass,FPGA_VCCIO1_3V3 local bypass,FPGA_VCCIO2_3V3 local bypass,FPGA_VCC_1V2 local bypass,LMX2592 reference-input AC coupling,LMX_REF_N local bypass,LMX_VTUNE local bypass,MAG_CT1 local bypass,MAG_CT2 local bypass,MAG_CT3 local bypass,MAG_CT4 local bypass,PHY_AVDDH_3V3 local bypass,PHY_AVDDL_1V2 local bypass,PHY_PLL_1V2 local bypass,USB_VBUS_SENSE local bypass |
| C9,C22,C63,C64,C68,C247,C271,C313,C323 | 1uF | +3V3_ANA local bypass,+3V3_DIG local bypass,FPGA_AUX_2V5 local bypass,FPGA_PLL_1V2 local bypass,LMX_VBIAS2 local bypass,LMX_VREG local bypass,LMX_VREG_IN local bypass,RP_CORE local bypass |
| C10,C315,C317,C320 | 2.2uF | +2V5_AUX local bypass,FPGA_VCCIO0_3V3 local bypass,FPGA_VCCIO1_3V3 local bypass,FPGA_VCCIO2_3V3 local bypass |
| C11,C12 | 4.7uF | +3V3_ANA local bypass,VIN_FUSED local bypass |
| C20,C21 | 15pF_C0G | RP_XIN local bypass,RP_XOUT local bypass |
| C70 | 4.7nF_C0G | LMX_CPOUT local bypass |
| C72,C156,C301 | 10nF | ADC_MODE local bypass,ADF_CC local bypass,PHY_PLL_1V2 local bypass |
| C74,C102,C211,C212 | 1nF_C0G | +3V3_ANA local bypass,ADF_CPOUT local bypass,ADL5801 driven RF input AC coupling,ADL_RF_UNUSED local bypass |
| C75 | 3.3nF_C0G | ADF_LF1 local bypass |
| C80,C201-C204,C206-C208,C210,C213,C215,C223,C232-C238,C245,C262,C268,C282 | 100pF_C0G | +3V3_ANA local bypass,+5V_RF local bypass,ADF4360-1 RF-output DC block,ADL_VSET local bypass,Differential anti-alias ladder shunt capacitor,GRF2013 input DC block,GRF2013 output DC block,GRF4001 2.3_4.2GHz input series match/DC block,GRF4001 input DC block,GRF4001 output DC block,LMX2592 RF-output DC block,LT5560 input AC coupling,LTC5548 RF-input DC block,LTC5548 single-ended LO-input DC block,PE4312 RF1 DC block; guarantees the required 0 VDC RF-port condition,PE4312 RF2 DC block; guarantees the required 0 VDC RF-port condition,Second GRF2013 output DC block |
| C157,C158 | 33pF_C0G | PHY_XI local bypass,PHY_XO local bypass |
| C205 | 15nF_C0G | ADF_VTUNE local bypass |
| C209,C219,C292,C2112 | 0.2pF_C0G | RF_HA_LNA_IN local bypass,RF_HD_LNA2_IN local bypass,RF_HD_LNA_IN local bypass,RF_LOW_LNA_IN local bypass |
| C216 | 0.6pF_C0G | GRF2101 4.2_6.8GHz input series match/DC block |
| C217 | 0.8pF_C0G | GRF2101 6.8_9.2GHz input series match/DC block |
| C218,C291 | 0.5pF_C0G | GRF2101 8.0_10GHz input series match/DC block,Second D-port GRF2101 8-10 GHz input series match |
| C246,C294,C2211 | 1.0pF_C0G | +3V3_ANA local bypass,LT_INPUT_SE local bypass |
| C264,C266 | 110pF_C0G | Differential anti-alias ladder shunt capacitor |
| C2110 | 22pF_C0G | RF_HB_LNA_IN local bypass |
| C2111 | 0.3pF_C0G | RF_HC_LNA_IN local bypass |
| C2210 | 2.2pF_C0G | +3V3_ANA local bypass |
| D1 | SMAJ5.0A | 400 W, 5 V unidirectional input TVS in the matching SMA package |
| D50,D60-D63 | PESD1V0R1BCSF | 0.1 pF RF-port ESD protection; avoids the multi-pF low-band TVS loss,0.1 pF RF-port ESD protection; placed before the input DC block |
| F1 | 2.5A_PTC | |
| FB1 | 600R@100MHz_2A | |
| FB30 | 600R@100MHz | |
| FB31-FB33,FB35-FB38 | 120R@100MHz | KSZ9031 AVDDH isolation required by the hardware design checklist,KSZ9031 AVDDL isolation required by the hardware design checklist |
| FB34 | 220R@100MHz | |
| FL50 | LFCN-2500+ | LTCC low-pass preselector; 0.1-2.5 GHz receive path |
| FL70 | QPQ1909TR13 | 2402.5-2493.5 MHz BAW filter; public five-pin pinout and complete 40 MHz channel |
| J1 | 5V_INPUT_ONLY | Regulated 5 V input, 3 A minimum; never connect ESC battery here |
| J10 | USB_B_Micro | USB data/control only; main board power is J1 |
| J11 | Cortex_SWD_10pin | |
| J30 | JK0654219NL | Integrated 1:1 magnetics and shielded RJ45; footprint is release-specific |
| J50 | RF_LOW_0.1_2.5GHz | Dedicated 100 MHz to 2.5 GHz edge-launch RF input |
| J60 | RF_HIGH_2.3_4.2GHz | Dedicated sub-band port removes a lossy/expensive 10 GHz input switch |
| J61 | RF_HIGH_4.2_6.8GHz | Dedicated sub-band port removes a lossy/expensive 10 GHz input switch |
| J62 | RF_HIGH_6.8_9.2GHz | Dedicated sub-band port removes a lossy/expensive 10 GHz input switch |
| J63 | RF_HIGH_8.0_10GHz | Dedicated sub-band port removes a lossy/expensive 10 GHz input switch |
| L1,L2 | 2.2uH_2.5A | |
| L80,L83 | 220nH | |
| L84,L97 | 33nH | |
| L85,L86 | 2.2uH | |
| L87,L88,L95,L96 | 200nH | |
| L89,L90,L93,L94 | 360nH | |
| L91,L92 | 390nH | |
| R1 | 453k_1% | |
| R2-R4 | 100k_1% | |
| R5 | 0 | |
| R20,R21 | 27R | |
| R22,R23,R144-R146 | 100k | |
| R30,R33,R134-R140,R148 | 4.7k | |
| R31,R50,R51,R120-R131,R149 | 33R | |
| R32,R60,R100,R105-R107,R111 | 0R | |
| R40 | 12.1k_1% | |
| R41,R141-R143,R147 | 10k | |
| R42,R43 | 330R | |
| R52-R55,R92 | 50R | |
| R56 | 68R_1% | |
| R58 | 4.7k_1% | |
| R59 | 620R_1% | |
| R61 | 1.5k_1% | |
| R70,R81 | 499R_1% | |
| R71 | 3.0R_1% | |
| R72 | 33R_1% | |
| R73,R74 | 25R_1% | |
| R75-R78 | 10k_1% | PE4312 pin 1 damping and maximum-attenuation power-up strap,PE4312 pin 3 package-resonance damping; place at the device |
| R79,R80 | 100R_1% | |
| R90 | 2.00k_1% | |
| R91 | 1.00k_1% | |
| R93-R95 | 51R | |
| R101 | 1.5k | |
| R102 | 200R | |
| R103,R112 | 2.9k | |
| R132,R133 | 2.2k | |
| SW1 | BOOTSEL | |
| SW2 | RESET | |
| T50 | 2450BL15B0200001E | Active 2.4-2.5 GHz 50-to-200 ohm balun; center-tap DC feed biases the ADL5801 IF outputs |
| T60 | TC1-1-13M+ | LTC5548 datasheet-recommended 1:1, 50 ohm differential-to-single-ended IF transformer |
| T70 | 2450BL15B0100001E | Active, low-cost 2.4-2.5 GHz 50-to-100 ohm input balun |
| Y10 | ABM8-272-T3_12MHz | 12 MHz, 10 pF load crystal |
| Y30 | ECS-250-20-33-TR_25MHz | 25 MHz, 20 pF, 40 ohm maximum-ESR PHY crystal |
| Y40 | SiT8209AC-23-33E-100.000000X | 100 MHz low-jitter 3.3 V reference oscillator; OE is asserted high |