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hprd
UT Austin Fall 2025-Spring 2026 Senior Design Project for developing a Zilog Z80 CPU drop-in replacement using an FPGA.
| Reference | Value | Description |
|---|---|---|
| U1 | L7805 | Positive 1.5A 35V Linear Regulator, Fixed Output 5V, TO-220/TO-263/TO-252 |
| U2 | Z80CPU | 8-bit General Purpose Microprocessor, DIP-40 |
| U3 | 74LS14 | Hex inverter schmitt trigger |
| U4 | 74LS02 | quad 2-input NOR gate |
| U5 | CY62256-70PC | 256K (32K x 8) Static RAM, 70ns, DIP-28 |
| U6 | LCD-16X2 | |
| U7 | SST39SF010 |
| Silicon Storage Technology (SSF) 128k x 8 Flash ROM |
| U8 | 74HC138 | 3-to-8 line decoder/multiplexer inverting, DIP-16/SOIC-16/SSOP-16 |
|---|
| U10 | 74HC244 | 8-bit Buffer/Line Driver 3-state |
|---|
| U11 | 74LS32 | Quad 2-input OR |
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| C1 | 330nF | Unpolarized capacitor |
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| C2-C4,C6-C13 | 100nF | Unpolarized capacitor |
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| C5 | 10uF | Unpolarized capacitor |
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| D25-D34 | LED | Light emitting diode |
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| DS1 | NHD-12864WG-BTMI-V#N | LCD MOD GRAPH 128X64 WH TRANSM |
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| J1,J3 | Conn_01x03_Pin | Generic connector, single row, 01x03, script generated |
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| J2 | PJ-102A | 2.0 mm Center Pin%2C 2.5 A%2C Right Angle%2C Through Hole%2C Tapered Pins%2C Dc Power Jack Connector |
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| J4-J7 | Conn_01x02_Pin | Generic connector, single row, 01x02, script generated |
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| J8 | Conn_01x16_Pin | Generic connector, single row, 01x16, script generated |
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| J9 | Conn_01x08_Pin | Generic connector, single row, 01x08, script generated |
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| R1,R8-R13,R15 | 1k | Resistor |
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| R3,R39-R50 | 1K | Resistor |
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| R4-R7 | 10K | Resistor |
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| RV1,RV2 | R_Potentiometer | Potentiometer |
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| SW1-SW8,SW10 | SW_Push | Push button switch, generic, two pins |
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| TP1-TP19 | TestPoint | test point |
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| Y1 | ACH-4.000MHZ-EK |
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