fujinet-hardware
FujiNetWIFI
Schematics and design files for FujiNet hardware
Components (36)
| Reference | Value | Description |
|---|---|---|
| Q1-Q3 | BC847 | BOOTSEL force (S3 GPIO5, Hi-Z idle),RUN force (S3 GPIO4, Hi-Z idle),console /RESET open-collector |
| U1 | RP2354A | RP2350A + 2MB stacked QSPI flash, QFN-60 |
| U2 | ESP32-S3-WROOM-1-N16R8 | 16MB QIO flash / 8MB octal PSRAM (IO35-37 NC) |
| U3 | CP2102N-A02-GQFN28 | USB-UART bridge (DevKitC-1 UART port) |
| U4 | UMH3N | auto-program: DTR/RTS -> EN/IO0 (DevKitC-1 circuit) |
| U5 | AP63203WU | 3.3V/2A sync buck (FB tied to VOUT: fixed 3.3V version) |
| C1,C2 | 15pF | crystal load |
| C3-C12,C19,C22,C23,C25,C26,C32 | 100nF | IO0 debounce,SD VDD decoupling,U1 decoupling,U2 decoupling,U3 decoupling,WS2812 decoupling,bootstrap |